Elik-tronics Solutions:
Hardware Engineer : Ask yourself the following questions :
- Do I really know why I use 50 Ohm Impedance ?? Why not 70 Ohm ?
- How do I avoid reflection ?
- Do I really know how to calculate crosstalk ?
- How to I start to route 2.5G trace over FR-4 PCB ?
Actually , Why not giving the experts to design my PCB ? I have to concentrate in the application !
- Today - more and more design involves Signal Integrity consideration :
Signal Integrity didn’t always matter. In the golden years of digital computing (1970-1990),
gates switched so slowly that, on the whole, digital signals actually looked like ones and zeros.
Analog modeling of signal propagation was not necessary. Unfortunately, those days are long gone.
At today’s
speeds even the simple, passive elements of a high-speed design—the wires, PC boards, connectors,
and chip packages— can make up a significant part of the overall signal delay. Even worse, these
elements can cause glitches, resets, logic errors, and other problems. As you push toward ever-higher
operating speeds, here’s a look at the primary issues you will face:
1) A greater percentage of PCB traces in new designs will likely require terminators. Terminators help control
ringing and overshoot on transmission lines. As speeds increase, more and more PCB traces will begin to take
on aspects of transmission line behavior, and thus will require terminators. Unfortunately, terminators occupy
precious space on every printed circuit board, and dissipate quite a bit of power. You will want to optimize the
use of terminators, placing them precisely where needed, and only where needed.
2) The exact delay of individual PCB traces will become more and more important. Already, CAD manufacturers are
beginning to incorporate features useful for matching trace lengths, and guaranteeing low clock skew.
At very high speeds,these features are crucial to system operation. You will want to master the study of
propagation delay in all its many forms.
3) Crosstalk will begin to overwhelm many systems. Every time the clock rate is doubled in a system, crosstalk
intensifies by a factor of two. This effect will bring some systems to their knees. Some of the symptoms
include flaky or data dependent logic errors, sudden system crashes, software branches to nowhere, impossible
state transitions, and unexplained interrupts. You will want to compress your layout to the maximum extent
possible (for cost reasons), but without compromising crosstalk on critical signals.
4) Ground bounce and power supply noise will boil over. Higher-powered drivers, switching at unbelievable rates,
in massive parallel bus structures, are a sure formula for a power system meltdown. Sure, throwing on more
pwr/gnd pins and more bypass capacitors helps, but where’s the limit? These things aren’t free. You will want
guaranteed glitch-free operation at a minimum cost.
Elik-tronics Solutions for Signal Integrity :
The PCB Layout department uses the best and the fast tools from Cadence®
Allegro® PCB and SPECCTRA® AutoRouter
Simulation - Done with SpecctraQuest ( Cadence® )